1. Field of the Invention
The present invention relates generally to semiconductor transistor devices. More specifically, the present invention relates to a vertical channel transistor device.
2. Description of the Prior Art
The planar transistor is often used as the basic devices in the semiconductor industry. In general, the so-called planar transistor has a gate channel parallel to a semiconductor substrate surface, and drain/source on the same surface of the semiconductor substrate in two sides of the gate channel. A gate dielectric layer is positioned on the gate channel, and usually a polycrystalline silicon gate is positioned on the gate dielectric layer. Furthermore, a spacer composed of dielectric materials is usually positioned on the sidewall of the polycrystalline silicon gate.
However, integrated circuit devices, especially the dynamic random access memory devices (DRAMs) are continually being made with higher device density, and since the conventional planar transistor requires more chip surface area, it does not fit in with the trend gradually. This problem can be temporarily resolved by shrinking the channel of the planar transistor, but it may result in leakage and short channel effect. Therefore, there is a strong need to provide an improved method for fabricating a transistor device in order to resolve the problems mentioned above.